A differential amplifier circuit is generally used in an output stage of a data line driver for driving data lines (i.e., signal lines) of a liquid crystal display panel. This is because the data lines provided in the liquid crystal display panel are long in length and have large parasitic capacities, and therefore large driving power is required for driving the data lines. Most typically, a voltage follower including a differential amplifier circuit is provided in the output stage so that the data lines are driven by the voltage follower.
In many cases, the differential amplifier circuit provided in the output stage of the data line driver is configured to adapt to a Rail-to-Rail operation. In other words, the differential amplifier circuit is configured in such a manner that a lower limit of a permissible range of input and output voltages is as near to a ground voltage as possible and an upper limit of the permissible range thereof is as near to a power supply voltage as possible. This requirement is particularly important to extend an operation voltage range in a case of a low power supply voltage.
One of the technical aspects to be taken into consideration in realizing the Rail-to-Rail operation is an operation voltage range of a differential pair including (an enhancement type of) NMOS transistor (to be referred to as “NMOS transistor pair” hereinafter) and of a differential pair including PMOS transistors (to be referred to as “PMOS transistor pair” hereinafter). The NMOS transistor pair is adapted for an input voltage equal to or higher than a threshold voltage VTN of the NMOS transistors and equal to or lower than the power supply voltage VDD. Whereas, the PMOS transistor pair is adapted for an input voltage equal to or higher than a ground voltage VSS and equal to or lower than (VDD−VTP), where VTP is a threshold voltage of the PMOS transistors.
In consideration of such characteristics of the transistors differential pair, the differential amplifier circuit performing the Rail-to-Rail operation is typically configured to include both of the NMOS transistor pair and the PMOS transistor pair. The differential amplifier circuit like this is disclosed in, for example, patent literature 1.
FIG. 1 is a circuit diagram showing a configuration of the differential amplifier circuit disclosed in the patent literature 1. In FIG. 1, the differential amplifier circuit 101 includes an NMOS transistor pair 102, a PMOS transistor pair 103, constant current sources IS1 and IS2, current mirrors 104 and 105, a floating current source 106, a constant current source IS3, a PMOS transistor MP8, an NMOS transistor MN8, and phase compensating capacitors C1 and C2. The NMOS transistor pair 102 includes a pair of NMOS transistors MN101 and MN102, and the PMOS transistor pair 103 includes a pair of PMOS transistors MP1 and MP2. Each of the current mirrors 104 and 105 is a folded-cascode type current mirror. The current mirror 104 includes PMOS transistors MP3 to MP6, and the current mirror 105 includes NMOS transistors MN3 to MN6. A bias voltage V1 is supplied to the PMOS transistors MP5 and MP6, and a bias voltage V2 is supplied to the NMOS transistors MN5 and MN6. The floating current source 106 includes a PMOS transistor MP7 and an NMOS transistor MN7. A bias voltage V3 is supplied to a gate of the PMOS transistor MP7, and a bias voltage V4 is supplied to a gate of the NMOS transistor MN7. A PMOS transistor MP8 and an NMOS transistor MN8 are connected in series between a power supply line 107 and a ground line 108, and they act as output transistors.
The differential amplifier circuit 101 configured as mentioned above generates an output voltage Vout corresponding to a difference between an input voltage In+ supplied to a non-inversion input terminal 109 and an input voltage In− supplied to an inversion input terminal 110, to output to an output terminal 111. Since the differential amplifier circuit 101 in FIG. 1 includes both of the NMOS transistor pair 102 and the PMOS transistor pair 103 in the input stage thereof, the Rail-to-Rail operation can be realized.
However, when the differential amplifier circuit 101 in FIG. 1 is used as a driver of a liquid crystal display panel, there arises a problem of aggravation of an amplitude difference deviation in a voltage range in the vicinity of the power supply voltage VDD or the ground voltage VSS although the Rail-to-Rail operation can be realized. Herein, the amplitude difference deviation means a deviation of a difference (amplitude difference) between a positive driving voltage and a negative driving voltage for the same gray scale when multiple differential amplifier circuits are provided. This problem is pointed out in patent literature 2. In this patent literature 2, it is concluded that a cause of aggravation of the amplitude difference deviation in a voltage range in the vicinity of the power supply voltage VDD or the ground voltage VSS is due to difference in the circuit operation between an intermediate voltage range and the voltage range in the vicinity of the power supply voltage VDD or the ground voltage VSS since the differential amplifier circuit 101 in FIG. 1 is provided with both of the NMOS transistor pair and the PMOS transistor pair (see Paragraph [0125] in the patent literature 2). Specifically, in the intermediate voltage range, both of the NMOS transistor pair and the PMOS transistor pair operate. Whereas, in the voltage range in the vicinity of the power supply voltage VDD, although the NMOS transistor pair operates, the PMOS transistor pair does not operate. Meanwhile, in the voltage range in the vicinity of the ground voltage VSS, while the PMOS transistor pair operates, the NMOS transistor pair does not operate. Switching in these operations causes an increase of an amplitude difference deviation in the voltage range in the vicinity of the power supply voltage VDD or the ground voltage VSS.
In the patent literature 2, as a measure for solving the problem of the amplitude difference deviation in the voltage range in the vicinity of the power supply voltage VDD or the ground voltage VSS, it is disclosed that only a differential pair of depletion-type NMOS transistors is used and a folded-type load circuit is further used as an active load. FIGS. 2 and 3 are circuit diagrams showing configurations of differential amplifier circuits 101A and 101B disclosed in the patent literature 2. The differential amplifier circuit 101A in FIG. 2 is configured to include a NMOS transistor pair 102A, a current mirror 104, constant current sources IS1 to IS3, and an output amplifier A1. The NMOS transistor pair 102A includes a pair of depletion-type NMOS transistors MN1 and MN2. Herein, each of the depletion-type NMOS transistors is depicted by adding a circle mark to a symbol of a usual NMOS transistor. Meanwhile, a folded cascode type current mirror is used as the current mirror 104 acting as an active load. It should be noted that a voltage source for supplying a bias voltage V1 is designated by a reference numeral 112 in FIG. 2. On the other hand, the differential amplifier circuit 101B in FIG. 3 is configured to include a NMOS transistor pair 102A, a current mirror 104, constant current sources IS1 to IS3, a floating current source 106, a current mirror 105A, a PMOS transistor MP8, and an NMOS transistor MN8. Also, in the circuit configuration in FIG. 3, a folded cascode type current mirror is used as the current mirror 104. Voltage sources for supplying the bias voltages V3 and V4 are respectively designated by reference numerals 114 and 115 in FIG. 3.
In the configurations shown in FIGS. 2 and 3, by using the NMOS transistor pair 102A including a pair of depletion-type NMOS transistors MN1 and MN2, a lower limit of the input voltage can adapt for the ground voltage VSS. Further, by using the folded cascode type current mirror 104 as a load circuit, a bias voltage required for operating the depletion-type NMOS transistors of the NMOS transistor pair 102A can be supplied even when the input voltage is in the voltage range in the vicinity of the power supply voltage VDD. Thus, the NMOS transistor pair 102A operates in the entire voltage range without occurrence of switching in the circuit operation. Therefore, according to the configurations shown in FIGS. 2 and 3, while the Rail-to-Rail operation can be realized, the amplitude difference deviation in the voltage range in the vicinity of the power supply voltage VDD and the ground voltage VSS can be reduced.
It should be noted that only the depletion-type NMOS transistor pair is provided in each of the configurations in FIGS. 2 and 3 without providing the PMOS transistor pair therein. The configuration disclosed in the patent literature 2 is based on a technical knowledge that only the depletion-type NMOS transistor pair is used in consideration of a defect that switching in the circuit operation occurs when the NMOS transistor pair and the PMOS transistor pair are both provided.
Citation List:
    [patent literature 1]: JP-A-Heisei 6-326529    [patent literature 2]: JP 2007-202127A